Move CPU Intensive Software Data Abstraction Functions to Hardware at 40, 80 or 100Gbps

Lossless packet capture and host CPU offload functions such as nanosecond timestamping are major challenges at high data rates. Moving CPU intensive software data abstraction functions to hardware at 40, 80 or 100Gbps rates is a cost effective way to achieve application performance.

Accolade’s line of FPGA-based 1-100GE host CPU Offload NICs and platforms enable 100% packet capture and nS timestamping as well as flow classification, deduplication, packet filtering and more.

100% Packet Capture

Each adapter port captures 100% of the incoming traffic, irrespective of packet size (i.e. 64 byte vs. jumbo frames), without dropping a single packet. Furthermore, line rate packet capture is supported irrespective of which packet processing functions (e.g. packet filtering) are enabled. Abundant onboard buffer memory is available to absorb abnormally large bursts of traffic.

Precise nS Timestamping

Each packet that enters an adapter is tagged with a timestamp with up to 4nS (nanosecond) time precision. The ANIC adapter has to be disciplined from a timing source and there are five options as follows listed in order of popularity:

1. Host OS – The host operating system acts as the time source and can in turn be disciplined by any other source such as PTP, 1PPS, NTP or the like.
2. GPS/CDMA – ANIC adapter can be directly attached (via a front port) to a 1PPS (One Pulse Per Second) time source such as GPS or CDMA.
3. PTP or IEEE 1588 – A PTP (Precision Time Protocol) network can be directly attached to an ANIC adapter via a front port.
4. Another ANIC adapter – One ANIC adapter can be the time source for another by attaching them via the onboard “card-to-card bus”.
5. Free Running – All timing is handled by the ANIC adapter onboard clock. This is the least precise mechanism but easiest to utilize.

An ANIC adapter can also parse out a Gigamon or Arista generated timestamp and propagate it forward to the host application.