Over the past several weeks I have been describing various features and functions of the ANIC series of host CPU offload adapters. The old saying that a picture is worth a thousand words also applies to ANIC features. So, this week, I am posting a diagram which we often use with customers to showcase the entire ANIC adapter pipeline. The heart of the adapter is an FPGA which houses all the various capabilities of the adapter.
When viewed from left to right, the diagram illustrates all the features and functions of each ANIC adapter after packets enter from one of the available interfaces (e.g. 1G, 10G or 100G). The very first function that is applied to each packet is a timestamp followed by various packet functions such as merging, parsing, slicing etc.
I won’t describe each feature here as I have been doing that in various blog posts in the past and will continue to do so in the coming weeks.
For a complete review of all ANIC adapter features please see below.