In the last few blog posts we have been talking about how Accolade ANIC SmartNICs use Xilinx FPGAs and the various advantages of FPGAs versus other technologies. One disadvantage of FPGAs is the relatively advanced skills required to program an FPGA. An FPGA is typically programmed using Verilog which isn’t a high-level programming language like C or Java but rather a hardware description language (HDL) used to model electronic systems. Accolade has many engineers (or “designers” as they prefer to be called) that are very experienced with Verilog because our greatest value add is the ability to provide sophisticated CPU offload functionality with FPGAs.
Typically, our end-customers are not well versed in Verilog and the last thing they want to do is actually develop a Verilog based design. However, on that rare occasion when a customer does have Verilog experience and actually wants or needs to do their own design, Accolade has put a process in place whereby customer specific Verilog code can be inserted directly into the adapter pipeline. One example, when this may be necessary is if the customer has a very secretive security algorithm or other proprietary techniques that they don’t want to expose to Accolade engineers.
To better understand how Accolade SmartNICs can help you succeed or to test drive one please contact us at firstname.lastname@example.org.