In order to support multi-core CPUs and multithreaded host applications, Accolade SmartNICs utilize a flexible HPB technique. Host memory is segmented into a number of fixed size blocks. The block size is configurable but is typically 2MB or 4MB each. A collection of these host memory blocks is then dynamically pooled together to form an HPB.
A specific application thread (often tied to a CPU core) is then explicitly assigned to a given HPB and will only process data that is “DMAed” into that HPB. Up to 64 independent HPBs can be created (per adapter) and in turn assigned to up to 64 host application threads.
Note that memory blocks assigned to an HPB do not have to be contiguous. In other words, each HPB is composed of blocks of host memory that are randomly spread out in various areas of physical host memory. In addition, memory blocks are temporarily assigned to a given HPB by the SmartNIC and once an application thread has finished processing all the data from a given memory block, that block can be assigned to a different HPB.
To test drive an Accolade SmartNIC please contact us at email@example.com