Host Packet Buffer (HPB)

Last week we talked about Direct Memory Access or DMA. Related to DMA is the concept of a Host Packet Buffer (HPB) which is a term coined by Accolade Technology.

In order to support multi-core CPUs and multithreaded host applications, ANIC adapters utilize a flexible HPB technique. Host memory is segmented into a number of fixed size blocks. The block size is configurable but is typically 2MB or 4MB each. A collection of these host memory blocks is then dynamically pooled together to form an HPB.

A specific application thread (often tied to a CPU core) is then explicitly assigned to a given HPB and will only process data that is “DMAed” into that HPB. Up to 64 independent HPBs can be created (per ANIC adapter) and in turn assigned to up to 64 host application threads.

Note that memory blocks assigned to an HPB do not have to be contiguous. In other words, each HPB is composed of blocks of host memory that are randomly spread out in various areas of physical host memory. In addition, memory blocks are temporarily assigned to a given HPB by the ANIC adapter and once an application thread has finished processing all the data from a given memory block, that block can be assigned to a different HPB.

For a complete review of all ANIC adapter features please see below.

Host CPU Offload Product Features Summary
wdt_ID Speed 1G 10G 10G 10G 10G/40G 10G/40G 100G 100G 100G 100G
1 Model ANIC-2KL
ANIC-4KL
ANIC-20Ku ANIC-40Ku ANIC-40Kq ANIC-80Ku ATLAS-1000
Platform
ANIC-100Ku ANIC-200Ku ANIC-
200KFlex
ANIC-200Kq
2 Port/Type 2 X 1G
4 X 1G
SFP
2 X 10G
SFP+
4 X 10G
SFP+
1 X 40G
4 X 10G
QSFP+
2 X 40G
8 X 10G
QSFP+
SFP+
2 X 40G
QSFP

4 X 10G
SFP+
1 X 100G
CFP4
2 x 100G
CFP4
2 x 40G
2 x 100G
QSFP28
2 x 100G
QSFP28
3 PCIe Interface Gen2 x8 Gen3 x8 Gen3 x8 Gen3 x8 Gen3 x8 Gen3 x8 Gen3 x16 Gen3 x16 Gen3 x16 Gen3 x16
4 Dimensions
(H x L inches)
4.25 x 6.25   4.25 x 6.25 4.25 x 6.25 4.25 x 6.25 4.25 x 6.25 1.75 x
12.28 x 14
4.25 x 10.5 4.25 x 10.5 4.25 x 6.5 4.25 x 10.5
5 Memory 256MB 4G 4G 4G 4G 16/32G 12G 12G 8G 12G
6 Timestamp 10 nS 5.7 nS 5.7 nS 5.7 nS 5.7 nS 5.7 nS 4 nS 4 nS 4 nS 4 nS
7 100% Packet
Capture
8 Gigamon,
Arista
Timestamp
9 Packet Merging
10 Packet Parsing

About Accolade

Accolade is the technology leader in FPGA-based Host CPU Offload and 100% Packet Capture PCIe NIC’s and Scalable 1U Platforms. Accolade’s line of 1-100GE products enable 100% packet capture, flow classification, flow shunting, deduplication, packet filtering and more. Our customers are global leaders in network monitoring & cybersecurity applications as well as in the network test and measurement, telecom and video stream monitoring markets.

FPGA Acceleration Features

100% Packet Capture | Flow Classification | Flow Shunting | Precise Time Stamping | Packet Merging | Packet Slicing | Packet Parsing | Packet Filtering | Deduplication | Host Packet Buffer | Packet Steering | Direct Memory Access (DMA) | Statistics (RMON1)

Free Product Evaluation

Resolve all your host CPU offload bottlenecks. Share Your Technical Requirements with our FPGA and software experts to tailor the optimal solution. Accolade offers a 60 day free product evaluation for qualified customers to fully test and evaluate our products.